Memory circuits, including, for example, dynamic random access memory (DRAM), are employed in a wide variety of devices and applications. As memory access time requirements are pushed faster and noise immunity requirements are increased, the design of memory circuit architectures to meet such requirements becomes significantly more challenging. Additionally, memory size requirements are continuously increasing, thereby exacerbating speed and noise immunity problems.
Various memory architectures have been proposed to meet certain design criteria, such as, for example, memory access time, often measured as latency. However, although these known memory architectures have had some successes at reducing memory latency, they have often achieved such a reduction in memory latency at the expense of other important design criteria, such as, for example, memory density, noise immunity, power consumption, etc., which are often mutually exclusive design characteristics in a given memory architecture.
Techniques for reliably sensing the logical states of memory cells in the memory circuit architectures also become more difficult to implement as memory performance requirements (e.g., memory access time, noise immunity, memory size, etc.) are pushed. For example, as voltage supply levels are reduced, sense amplifiers in the memory circuits are significantly more sensitive to threshold variations and mismatch. In order to minimize threshold mismatch in the sense amplifiers, it is known to increase transistor dimensions. However, increasing the transistor dimensions increases the overall chip area required by the memory circuits, and is therefore undesirable.
Accordingly, there exists a need for sensing circuitry for use in a memory circuit that does not suffer from one or more of the problems exhibited by conventional sensing circuitry.